The present invention relates generally to semiconductor devices and, more particularly, to techniques for analyzing and debugging circuitry associated with an integrated circuit.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A requirement of such high-density and high functionality in semiconductor devices has been the demand for increased density of individual circuitry within the chip. The increased density permits shorter electrical connections between the devices than possible in chips manufactured with circuitry in a less-dense arrangement.
A by-product of increased circuit density and decreased chip size is the occurrence of a condition known as xe2x80x9clatch-up.xe2x80x9d Latch-up is an undesirable and sometimes self-destructive phenomenon that occurs when an inadvertent low-resistance path is created between power supply nodes (often referred to as VDD and VSS) in a semiconductor device. An inadvertent low-resistance path can pass current at levels that exceed the tolerance of the circuitry carrying the path. Consequently, such large currents can generate high levels of heat, ultimately resulting in cessation of circuit functions and even permanent destruction of the circuit.
Latch-up typically occurs as a result of the proximate locations of circuits, circuit components as well as portions of circuit components, due to the high-density requirements of semiconductor devices. For example, in the design of complimentary metal-oxide semiconductor (CMOS) devices, there are complementary parasitic bipolar transistor structures that are in close proximity to one another. The close proximity allows the complimentary parasitic bipolar structures to interact electrically to form device structures that behave like pnpn diodes. Normally, such diodes are reverse-biased. However, in the presence of certain operating conditions, such as transient displacement currents, terminal over-voltage stress, ionizing radiation, or impact ionization by hot electrons, a normally reverse-biased diode becomes a forward-biased diode. Once the device becomes forward biased, current flows freely between the nodes of the device. As long as sufficient power is supplied, the device remains in the xe2x80x9cONxe2x80x9d state and exhibits latch-up.
The cause of a latch-up condition in a CMOS device has been studied for some time. According one theory based on the principles of pnpn diode operation, each of four conditions exists in a CMOS circuit for latch-up to occur. These conditions are: 1) the emitter-base junctions of both parasitic bipolar transistors are forward biased; 2) the mathematical product of current gains is sufficiently large for regenerative feedback; 3) the external circuit supplies a voltage that is at least equal to the structure""s holding voltage; and 4) a latch-up stimulus is present for at least a minimum latch-up trigger time. Attempts to alleviate the latch-up problem have included various ways to prevent one or more of these above conditions from occurring. For details concerning the mathematics of, and efforts to overcome, the latch-up problem, reference may be made to various references such as R. R. Troutman, Latchup in CMOS Technologyxe2x80x94The Problem and its Cure, Kluwer Academic Publishers, Boston, Mass., 1986, and S. Wolf, Silicon Processing for the VLSI Eraxe2x80x94Volume 11, Lattice Press, Sunset Beach, Calif. 1990, each of which is incorporated herein by reference. While the attempts to overcome and test for latch-up have been successful to various levels of degree, as addressed in the above-cited references, the latch-up problem is evolving by taking on new forms as the semiconductor industry continues to increase circuit density by shrinking device dimensions. For this reason, it is difficult to ensure that latch-up will not occur for each new design.
Newly designed high-density ICs, such as flip chips, PGAs and DIPs have circuits exposable from a substrate backside. For such circuits, testing for latch up is difficult, however, being able to effectively test the IC for circuit areas that might be more susceptible to latch-up is still an important part of the testing process. This is especially true in highly-competitive market environments where product-development costs play an important role in the success of new products. For IC circuit areas that are susceptible to latch-up, it is important that product-development efforts be able to quickly detect these circuit areas.
Heretofore, efforts to induce latch-up have been largely directed to studying how the above four conditions can be readily induced to effect a latch-up condition. Based on this information, conventional approaches to inducing latch-up are largely directed to providing stimulus at input/output ports of the IC. Effectively inducing a latch-up condition for a particular IC provides the IC designer with the knowledge that the IC design should be reevaluated. This feedback to the IC designer is lacking, however, in that the IC designer must reevaluate the IC design without necessarily knowing the specific location of the latch-up. Consequently, the IC designer is left with the burden of reevaluating many circuits that are unrelated to the cause of the detected latch-up condition.
Accordingly, semiconductor technology would benefit from an approach that effectively detects and locates that circuitry that is susceptible to latch-up conditions. The ability to detect the location of latched-up circuitry in highly-integrated circuits can be a significant step in reducing the engineering-development time, reducing or possibly eliminating the existence of such defective devices in the market and thereby reducing the overall cost of products in the marketplace.
The present invention is directed to methods and apparatuses involving the detection of a latch-up condition in a semiconductor device. In one example method embodiment, a latch-up condition is detected in a semiconductor device, via its back side, by blasting a surface of the device with electron-hole pairs sufficient to create latch-up in sensitive circuits. The device is then analyzed and, if a latch-up condition is present, it is detected as part of the analysis.
According another example embodiment, a latch-up condition in a semiconductor device is detected by using of a laser beam to scan through the backside of the semiconductor device to ascertain an intensity threshold that is known to cause latch-up conditions. The intensity of the beam is then decreased and the beam of decreased intensity is applied to a designated region within the semiconductor device. A latch-up condition present at the designated region is then detected using conventional microscopy equipment. Latched-up circuits in such designated regions are designated as being overly sensitive.
In another example embodiment, a method for detection of a latch-up condition of a semiconductor device is provided. The backside of the semiconductor device is scanned with a laser beam having an upper intensity that does not cause latch-up conditions. The intensity of the beam is then increased to another intensity to cause latch-up conditions in certain circuit areas. These circuit areas may then be used as areas for further evaluation in connection with design improvements.
In another example embodiment, a system is provided to detect a latch-up condition in a semiconductor device. The system comprises means for applying a beam, means for securing the semiconductor device so that the beam can scan through the backside of the semiconductor device at a first intensity, and means for indicating if a latch-up condition is present in response to an increased intensity of the beam over a designated region of the semiconductor device.
In yet another example embodiment, a system detects a latch-up condition in a semiconductor device using a laser device that is adapted to apply an energy field. The system includes a fixture for securing the semiconductor device so that the laser device can scan through the backside of the semiconductor device at a first intensity. A processor arrangement, including a computer, is configured and arranged to indicate automatically whether a latch-up condition is present in response to an increased intensity of the laser beam over a designated region of the semiconductor device.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.